CS27: Systems Architecture
CPU components, buses, registers, the fetch-decode-execute cycle, and factors affecting processor performance.
📋 CPU Components
Definition: The CPU (Central Processing Unit) is the brain of the computer. It processes data by executing instructions. The CPU contains the ALU, control unit, clock, and registers, connected by internal buses.
ALU (Arithmetic Logic Unit)
The ALU performs all calculations and logical operations:
- Arithmetic operations: addition, subtraction, multiplication, division
- Logic operations: comparisons (equal to, greater than, less than), AND, OR, NOT
- Produces results that are stored in the accumulator (ACC)
- Sets status flags based on results (zero flag, carry flag, negative flag)
Control Unit (CU)
The control unit coordinates all activities within the CPU:
- Directs the flow of data between the CPU and other components
- Controls the fetch-decode-execute cycle
- Sends control signals to other components
- Decodes instructions fetched from memory
- Tells the ALU what operation to perform
- Manages timing of all CPU operations using the clock
Clock
The clock generates regular pulses that synchronise all CPU operations:
- Each pulse is one "tick" of the clock
- Clock speed is measured in GHz (gigahertz) - billions of ticks per second
- Each instruction takes one or more clock cycles to complete
- Higher clock speed = more instructions per second = faster processing
- A 3 GHz CPU ticks 3 billion times per second
📝 CPU Registers
Definition: Registers are small, very fast memory locations inside the CPU. They hold data and instructions currently being processed. Registers are the fastest type of memory in a computer system.
| Register | Full Name | Function |
|---|---|---|
| PC | Program Counter | Holds the memory address of the NEXT instruction to be fetched |
| MAR | Memory Address Register | Holds the address in memory that is about to be read from or written to |
| MDR | Memory Data Register | Holds the data that has been read from or is about to be written to memory |
| ACC | Accumulator | Holds the results of calculations performed by the ALU |
| CIR | Current Instruction Register | Holds the instruction that is currently being decoded and executed |
How Registers Work Together
When the CPU needs to fetch an instruction:
1. The PC holds the address of the next instruction (e.g. 100)
2. This address is copied to the MAR
3. The instruction at that address is loaded into the MDR
4. The instruction in the MDR is copied to the CIR for decoding
5. The PC is incremented to point to the next instruction (e.g. 101)
🚌 System Buses
Definition: Buses are parallel wires that connect components of the computer system, allowing data, addresses, and control signals to move between them.
Address Bus
- Carries memory addresses from the CPU to memory
- Unidirectional - signals travel from CPU to memory only
- The CPU places the address it wants to access on this bus
- Width determines how much memory can be addressed (e.g. 32-bit bus = 232 addresses)
Data Bus
- Carries data between the CPU, memory, and I/O devices
- Bidirectional - data flows both ways
- Carries instructions read from memory AND results written back to memory
- Width determines how much data can be transferred at once (e.g. 64-bit bus = 64 bits at a time)
Control Bus
- Carries control signals from the CPU to coordinate activities
- Bidirectional - some signals go both ways
- Key signals: Read/Write (determines if memory is read or written), Clock (synchronises timing), Interrupt (signals that need attention)
| Bus | Carries | Direction |
|---|---|---|
| Address Bus | Memory addresses | Unidirectional (CPU → memory) |
| Data Bus | Data and instructions | Bidirectional |
| Control Bus | Control signals (read, write, clock) | Bidirectional |
🔄 The Fetch-Decode-Execute Cycle
Definition: The fetch-decode-execute cycle (also called the instruction cycle) is the process the CPU follows for every instruction. It fetches the next instruction from memory, decodes it to understand what to do, then executes it.
Fetch Phase
- The address in the PC is copied to the MAR via the address bus
- The instruction stored at that memory address is copied to the MDR via the data bus
- The instruction in the MDR is copied to the CIR
- The PC is incremented by 1 (to point to the next instruction)
Decode Phase
- The control unit decodes the instruction in the CIR
- It identifies the operation (opcode) and any data needed (operand)
- The control unit prepares the necessary signals and pathways
Execute Phase
- The instruction is executed (e.g. a calculation by the ALU)
- Results may be stored in the ACC or written back to memory
- If data needs to be read from or written to memory, the MAR and MDR are used again
Example: ADD 5
Fetch: PC holds address 50. Address 50 is copied to MAR. The instruction "ADD 5" at address 50 is copied to MDR, then to CIR. PC is incremented to 51.
Decode: The CU decodes "ADD 5" - it identifies this is an addition operation with the value 5.
Execute: The ALU adds 5 to the current value in the ACC. The result is stored in the ACC.
Fetch-Decode-Execute Summary:
Fetch: PC → MAR → (memory) → MDR → CIR; PC++
Decode: CU interprets instruction in CIR
Execute: ALU performs operation; result stored in ACC or memory
The cycle repeats continuously while the computer is running
Fetch: PC → MAR → (memory) → MDR → CIR; PC++
Decode: CU interprets instruction in CIR
Execute: ALU performs operation; result stored in ACC or memory
The cycle repeats continuously while the computer is running
⚡ Factors Affecting CPU Performance
Clock Speed
Key Concept: Clock speed determines how many instruction cycles the CPU can perform per second. A higher clock speed means more instructions can be processed in the same time.
- Measured in GHz (billions of cycles per second)
- Higher clock speed = more cycles per second = faster processing
- Overclocking increases clock speed beyond the rated speed but generates more heat
- Higher clock speeds increase power consumption and heat output
Number of Cores
Key Concept: A core is a complete processing unit within the CPU. A multi-core processor has multiple cores that can execute instructions simultaneously.
- Dual-core = 2 cores, Quad-core = 4 cores, Octa-core = 8 cores
- More cores can process multiple instructions at the same time (parallel processing)
- However, doubling cores does NOT double speed - not all tasks can be split across cores
- Some software is not written to take advantage of multiple cores
Example
A quad-core 2 GHz CPU does NOT run at 8 GHz. Each core runs at 2 GHz but can work on different tasks simultaneously. If a task can be split into 4 independent parts, it could complete up to 4 times faster. But many tasks must be done sequentially and cannot be split.
Cache Size
Key Concept: Cache is a small, very fast memory between the CPU and RAM. It stores frequently used data and instructions so the CPU can access them quickly without waiting for RAM.
- L1 cache: smallest, fastest, inside the CPU core
- L2 cache: larger, slightly slower, per core or shared
- L3 cache: largest, slowest (but still faster than RAM), shared across cores
- Larger cache = more data available quickly = fewer slow trips to RAM = better performance
- Cache hit = data is in cache (fast); Cache miss = data must be fetched from RAM (slow)
| Factor | How It Improves Performance | Limitation |
|---|---|---|
| Higher clock speed | More cycles per second | More heat, more power consumption |
| More cores | Parallel processing of multiple tasks | Not all software uses multiple cores; diminishing returns |
| Larger cache | Fewer slow accesses to RAM | More expensive; larger cache is slightly slower |
⚠️ Common Mistakes to Avoid
| Mistake | Why It's Wrong | How to Fix It |
|---|---|---|
| Saying "the PC holds the current instruction" | PC holds the address of the NEXT instruction | PC = next; CIR = current |
| Saying "more cores = faster speed" | More cores = more parallel tasks, not faster clock | More cores allow parallel processing, not higher speed |
| Confusing MAR and MDR | MAR holds addresses; MDR holds data | MAR = Memory Address Register (where); MDR = Memory Data Register (what) |
| Saying "the data bus is unidirectional" | Data must flow both ways (read and write) | Data bus is bidirectional; address bus is unidirectional |
| Forgetting to increment the PC | The PC must move to the next instruction | Always mention "PC is incremented" in the fetch phase |
❓ Practice Questions
Q1: Describe the role of each of the following CPU components: ALU, Control Unit, PC, MAR, MDR, ACC.
Q2: Explain the three stages of the fetch-decode-execute cycle.
Q3: How does increasing the number of cores affect CPU performance? Why doesn't doubling the cores double the speed?
Q4: What is the purpose of cache memory? Why does a larger cache improve performance?
Q5: State whether each bus is unidirectional or bidirectional: address bus, data bus, control bus.
✅ Answers
- ALU: performs arithmetic and logic operations. Control Unit: coordinates all CPU activities, decodes instructions. PC: holds the memory address of the next instruction to fetch. MAR: holds the memory address to read from or write to. MDR: holds the data being read from or written to memory. ACC: stores the results of ALU calculations.
- Fetch: the address in the PC is copied to the MAR, the instruction at that address is copied to the MDR, then to the CIR, and the PC is incremented. Decode: the control unit decodes the instruction in the CIR to identify the operation and operands. Execute: the instruction is carried out (e.g. ALU performs calculation) and results are stored in the ACC or written to memory.
- More cores allow the CPU to process multiple instructions simultaneously (parallel processing). However, doubling cores does not double speed because: not all tasks can be divided into parallel parts, some software is not written to use multiple cores, and cores share some resources (cache, bus bandwidth).
- Cache stores frequently used data and instructions close to the CPU, providing faster access than RAM. A larger cache holds more frequently used data, reducing cache misses (times the CPU must wait for data from slower RAM). Fewer cache misses = less wasted time = better performance.
- Address bus: unidirectional (CPU to memory). Data bus: bidirectional. Control bus: bidirectional.
🎯 Exam Tips
- Know all CPU components and registers with their full names and functions
- Be able to describe the fetch-decode-execute cycle step by step
- Remember: PC = next instruction address, CIR = current instruction, ACC = calculation result
- For performance questions, discuss clock speed, cores, AND cache
- Never say "more cores = double the speed" - explain parallel processing carefully
- Know the direction of each bus: address = one way, data and control = both ways
⚠️ Common Errors
✗ Confusing the ALU and the CU within the CPU ✓ The ALU (Arithmetic Logic Unit) performs calculations and logical comparisons. The CU (Control Unit) manages and coordinates all CPU activities, decoding instructions and sending control signals.
✗ Thinking more cores always means faster performance for all programs ✓ More cores improve performance for programs designed to split work across cores (parallel processing). Single-threaded programs only use one core, so extra cores provide no benefit.
✗ Believing cache memory is the same as RAM ✓ Cache is much smaller, faster, and more expensive than RAM. It sits between the CPU and RAM, storing frequently used instructions/data to reduce access time.
✗ Forgetting the Fetch-Decode-Execute cycle order ✓ The cycle is always: 1) FETCH the next instruction from memory, 2) DECODE what the instruction means, 3) EXECUTE the instruction. Then repeat.
✍️ Model Answer
Full-Mark Response
Describe the role of the CPU in the Fetch-Decode-Execute cycle, explaining the purpose of the Program Counter, Memory Address Register, and Accumulator. [5 marks]
The CPU continuously performs the Fetch-Decode-Execute cycle: FETCH: The Program Counter (PC) holds the address of the next instruction. This address is copied to the Memory Address Register (MAR). The instruction at that address is fetched from RAM and stored in the Memory Data Register (MDR). The PC is then incremented to point to the next instruction. DECODE: The Control Unit (CU) decodes the fetched instruction to determine what operation to perform and what data is needed. EXECUTE: The Arithmetic Logic Unit (ALU) performs any calculations or logic operations. The result is stored in the Accumulator (a special register that holds the results of arithmetic/logic operations). If needed, the result may be stored back in RAM. The cycle then repeats from FETCH.
📊 AO Deep Dive
Assessment Objective Analysis
AO1 (Computational Thinking — 40%): Demonstrate knowledge and understanding of the principles and concepts of computer science, including systems architecture: CPU components and the fetch-decode-execute cycle for AQA 8525, OCR J277 & Edexcel 1CP2.
AO2 (Application — 40%): Apply knowledge and understanding of computer science, including systems architecture: CPU components and the fetch-decode-execute cycle to analyse problems in computational terms and to design, write and evaluate solutions.
AO3 (Evaluation — 20%): Evaluate the effectiveness, correctness and efficiency of computational solutions, including systems architecture: CPU components and the fetch-decode-execute cycle, and make reasoned judgements about trade-offs.
📝 Exam Technique
GCSE Computer Science Exam Tips:
CPU components: ALU (calculations), CU (control/decode), registers (PC, MAR, MDR, Accumulator). FDE cycle: Fetch → Decode → Execute — always in this order. PC = next instruction address. MAR = address to access. MDR = data at that address. Accumulator = calculation results. Cache: fast, small, expensive. More cores = parallel processing benefit only. Clock speed = cycles per second.
CPU components: ALU (calculations), CU (control/decode), registers (PC, MAR, MDR, Accumulator). FDE cycle: Fetch → Decode → Execute — always in this order. PC = next instruction address. MAR = address to access. MDR = data at that address. Accumulator = calculation results. Cache: fast, small, expensive. More cores = parallel processing benefit only. Clock speed = cycles per second.
📝 Exam Questions by Topic
🎬 Video Resources
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