E9: Sequential Logic & Flip-Flops
SR latch, D flip-flop, JK flip-flop, counters and shift registers
Sequential Logic & Flip-Flops
SR latch, D flip-flop, JK flip-flop, counters and shift registers
Key Fact: Sequential logic circuits have memory; their output depends on both current inputs and previous states.
Key Fact: An SR latch (Set-Reset) is the simplest memory element, built from two cross-coupled NAND or NOR gates.
Key Fact: The SR latch using NOR gates: S=1,R=0 sets Q=1; S=0,R=1 resets Q=0; S=0,R=0 holds state; S=1,R=1 is invalid.
Key Fact: A D flip-flop (data) captures the D input value on the clock edge; Q follows D when clocked.
Key Fact: A JK flip-flop generalises the SR latch: J=1,K=0 sets; J=0,K=1 resets; J=0,K=0 holds; J=1,K=1 toggles.
Key Fact: The toggle feature of JK flip-flops (J=1,K=1) makes them ideal for building binary counters.
Key Fact: Counters can be asynchronous (ripple) or synchronous; synchronous counters use a common clock for all flip-flops.
Key Fact: An n-bit binary counter counts from 0 to 2ⁿ − 1 and then rolls over; a modulo-N counter resets after N.
Key Fact: A shift register stores and shifts data left or right on each clock pulse; used for serial-parallel conversion.
Key Fact: Flip-flops can be edge-triggered (responding to clock transitions) or level-triggered (responding while clock is high).
Key Fact: A register file is a collection of flip-flops used to store multiple bits of data simultaneously.
Key Fact: Timing diagrams show the relationship between clock, input and output signals over time.
📋 Key Vocabulary and Concepts
For Sequential Logic & Flip-Flops, you must know:
- Flip-flop: A clocked bistable memory element that stores one bit of data and changes state on a clock edge.
- SR latch: A Set-Reset bistable circuit that stores one bit; the simplest sequential logic element.
- Edge-triggered: A flip-flop that responds to its inputs only at the moment of a clock transition (rising or falling edge).
- Toggle: When J=K=1, the JK flip-flop inverts its output on each clock pulse.
- Ripple counter: An asynchronous counter where each flip-flop's clock comes from the output of the previous stage.
- Shift register: A chain of flip-flops that moves stored data one position left or right on each clock pulse.
❓ Practice Questions
Q: What is the invalid condition for an SR latch built from NOR gates?
Q: How does a D flip-flop differ from an SR latch?
Q: What happens when J=1 and K=1 on a JK flip-flop?
Q: How many flip-flops are needed for a modulo-16 counter?
Q: What is the difference between a ripple counter and a synchronous counter?
✅ Answers
- S=1 and R=1 simultaneously, because both Q and Q' would be forced to 0, violating the bistable condition.
- A D flip-flop is clocked and edge-triggered; it captures the D input on the clock edge, eliminating the invalid state and timing problems of an SR latch.
- The output toggles: Q becomes the complement of its previous value on each clock pulse.
- 4 flip-flops, since 2⁴ = 16 states (counting 0 to 15).
- In a ripple counter, each flip-flop is clocked by the output of the previous stage (asynchronous); in a synchronous counter, all flip-flops share a common clock.
🎯 Exam Tips
- Draw truth/characteristic tables for flip-flops showing all input combinations and resulting Q.
- For counter design, determine the number of flip-flops from n = ⌈log₂(N)⌉ for a modulo-N counter.
- Always show the clock signal on timing diagrams and mark the triggering edge.
- State the invalid condition for SR latches and explain why JK flip-flops avoid it.
- For shift register questions, show data movement step by step with each clock pulse.
📝 Exam Technique
GCSE Electronics Exam Tips — Sequential Logic & Flip-Flops:
1. For Sequential Logic & Flip-Flops questions, use correct electronic symbols and terminology
2. Always show your working in calculations, including units at each step
3. When analysing circuits, state which law or rule you are applying first
4. For evaluation questions on Sequential Logic & Flip-Flops, compare component choices and consider cost, reliability and tolerance
5. Draw circuit diagrams neatly with conventional symbols
1. For Sequential Logic & Flip-Flops questions, use correct electronic symbols and terminology
2. Always show your working in calculations, including units at each step
3. When analysing circuits, state which law or rule you are applying first
4. For evaluation questions on Sequential Logic & Flip-Flops, compare component choices and consider cost, reliability and tolerance
5. Draw circuit diagrams neatly with conventional symbols
⚠️ Common Errors
✗ Allowing S=1 and R=1 on an SR latch as a normal operating condition. ✓ S=1,R=1 is the invalid/forbidden state; it violates the bistable condition. Use a JK flip-flop instead, which handles J=1,K=1 as a toggle.
✗ Confusing level-triggered and edge-triggered flip-flop behaviour. ✓ Level-triggered devices respond while the clock is at a level; edge-triggered devices respond only at the instant of the clock transition.
✗ Forgetting to account for propagation delay in ripple counters. ✓ Ripple counters have cumulative delay since each stage waits for the previous one; synchronous counters avoid this with a common clock.
✗ Drawing fewer flip-flops than needed for a counter's modulus. ✓ A modulo-N counter needs ⌈log₂(N)⌉ flip-flops; e.g. modulo-10 needs 4 flip-flops (2⁴ = 16 ≥ 10).
✍️ Model Answer
Full-Mark Response
Explain the operation of SR, D and JK flip-flops, and describe how JK flip-flops are used to construct a binary counter.
An SR latch has two inputs: Set (S) and Reset (R). Setting (S=1, R=0) makes Q=1; resetting (S=0, R=1) makes Q=0; S=0, R=0 holds the previous state; S=1, R=1 is invalid because both Q and Q' would be 0. A D flip-flop has a single data input D and a clock. On the active clock edge, Q takes the value of D. This eliminates the SR invalid state since only one input determines the next state. A JK flip-flop has J and K inputs: J=1,K=0 sets; J=0,K=1 resets; J=0,K=0 holds; J=1,K=1 toggles the output. The toggle mode is unique to the JK flip-flop and makes it ideal for counters. A binary counter is built by connecting JK flip-flops with J=K=1 (toggle mode). The first flip-flop toggles on every clock pulse (LSB). Its Q output clocks the next flip-flop, which toggles at half the rate, and so on. This creates a ripple counter that counts in binary from 0 to 2ⁿ−1. For a synchronous counter, all flip-flops share the same clock, and J-K inputs are driven by logic that enables toggling at the correct counts, eliminating ripple delay.
📊 AO Deep Dive
Assessment Objective Analysis
AO1 (Knowledge & Understanding): Demonstrate knowledge and understanding of sequential logic & flip-flops, including electronic components, circuit theory and systems concepts relevant to WJEC Eduqas C690QS.
AO2 (Application): Apply knowledge and understanding of sequential logic & flip-flops to analyse, design and construct electronic circuits and systems.
AO3 (Evaluation): Evaluate electronic circuits and systems, making reasoned judgements about design choices, performance and practical considerations, constructing supported arguments.
📝 Exam Questions by Topic
🎬 Video Resources
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