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Computer Systems and Architecture

Year 1 / ASYear 2 / A-Level All Boards (AQA, Edexcel, OCR, WJEC, CCEA) AQA

A-Level Computer Science revision: Computer Systems and Architecture. Learning objectives, key points, worked examples and practice questions across AQA, Edexcel, OCR, WJEC and CCEA.

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📌 Key Points

Key Fact: CPU: ALU (arithmetic/logic), CU (control signals), Registers: PC (next instruction), ACC (results), MAR (address), MDR (data), CIR (instruction), SR (flags)
Key Fact: FDE: Fetch (PC to MAR, memory to MDR/CIR, PC++), Decode (CU interprets CIR), Execute (ALU/control)
Key Fact: Pipelining: fetch/decode/execute overlap; hazards (data, control, structural)
Key Fact: Memory: Registers > L1 cache > L2 > L3 > RAM > SSD > HDD; Virtual memory: paging, page table, TLB, page fault
Key Fact: CISC: complex instructions, variable length, microcode; RISC: simple, fixed length, load/store, more registers
Key Fact: Parallel: SIMD (single instruction, multiple data), MIMD (multicore); Amdahl: speedup = 1/((1-p) + p/n)

🎯 Learning Objectives

  • Explain CPU architecture: ALU, CU, registers (PC, ACC, MAR, MDR, CIR, SR)
  • Describe fetch-decode-execute cycle and pipelining
  • Understand memory hierarchy: registers, cache (L1/L2/L3), RAM, virtual memory, secondary storage
  • Compare CISC vs RISC, parallel processing (SIMD, MIMD, multicore)
  • Understand instruction sets: addressing modes, instruction formats, assembly basics
  • Analyse performance: clock speed, CPI, IPC, Amdahl's law

💡 Worked Example

Exam-Style Question

Question: A program has 20 percent serial code. Max speedup on 4 cores?

Model Answer:

Amdahl: speedup = 1/((1-0.8) + 0.8/4) = 1/(0.2 + 0.2) = 2.5x. Even infinite cores: 1/0.2 = 5x

❓ Practice Questions

Questions:

  • List registers and their purposes
  • Draw FDE cycle diagram
  • Explain cache hit/miss
  • Compare CISC vs RISC
  • Calculate speedup: 30 percent serial, 8 cores

🎬 Video Resources

📄 Past Papers & Exam Resources

🔗 Further Reading & Resources