Homeschool Guide: These lesson plans are a guide for parents. Content may contain errors — always cross-reference with official exam board specifications.

EL2: Combinational Logic Design

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4 detailed 50-minute lessons with teaching scripts, worked examples, parent guides, and assessment criteria.

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Lesson Overview

Total Lessons: 4
Tier: Foundation and Higher
Duration: 50 minutes per lesson (200 minutes total)
Exam Boards: Eduqas

Learning Objectives

Prerequisites

Materials & Equipment

Lesson 1: Introduction: Combinational Logic Design

Duration: 50 minutes

Starter Activity (5 minutes)

Quick Recall

3 quick questions to activate prior knowledge about combinational logic design. Use mini-whiteboard or paper.

Main Content (35 minutes)

Parent/Teacher Guide:
Before lesson: Read script below. Prepare materials. Pre-teach key vocab: Combinational Logic Design.
If stuck: See Troubleshooting below. Break into smaller steps.
Extension: See Stretch & Challenge section.
Teaching Script (35 mins):
Mins 0-5 - Hook: "Today: Combinational Logic Design. Goal: by the end you can ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit, using the method shown step by step. Connects to the previous lesson in this unit because you'll reuse its method throughout today's work."
Mins 5-15 - Direct Instruction: 1) Define: "Combinational Logic Design is..." 2) Key principle: "Most important:..." 3) Draw diagram, label live. 4) Real example: "Like ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit. - a real example worked through in full..."
Mins 15-25 - Guided Practice: Ex1: Teacher models. Ex2: Student tries with guidance. Ex3: Student independent.
Mins 25-35 - Independent Practice: 3-5 questions. Immediate feedback.
Worked Example 1: Basic

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. What is asked? Explain
  2. Recall knowledge:
  3. Apply: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous stage, creating a ripple delay proportional to the number of bits.
  4. Check: Check the units named in the question and sense-check the size of your answer.
  5. Answer: State the complete final answer.

Tip: "Show working - method marks > answer marks."

Worked Example 2: Multi-step

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Break down: Separate parts?
  2. Solve each: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous
  3. Combine: The parts chain: each answer feeds the next step of the question.
  4. Final answer: Evidence cited from the lesson content.
Worked Example 3: Data/Application

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Read data: Axes, units, scale
  2. Patterns: Trends, anomalies
  3. Explain: Why? Using combinational logic design
  4. Conclude: Evidence-based

Common Questions & Troubleshooting

Q: "Why does Combinational Logic Design work this way?"
A: Analogy: "✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.". Try re-draw or re-write the worked example from memory, then check it against the model answer.
Q: "Wrong answers on calculations."
A: Checklist: units? formula? calculator mode? sig figs?
Q: "Can't remember key terms."
A: Flashcards (term front, def+diagram back). Spaced repetition: day 1, 3, 7.
Q: "Exam wording confuses me."
A: Commands: Describe=what you see; Explain=reasons; Evaluate=pros/cons+judgement; Calculate=working+units.
Q: "Running out of time."
A: 1 mark/min. Skip hard, return. Attempt all - partial marks count.

Assessment & Model Answers

Mastery Checklist:
  • [ ] Define Combinational Logic Design in own words
  • [ ] Identify features in diagram
  • [ ] Explain process step-by-step
  • [ ] Apply to unfamiliar context
  • [ ] Score 80%+ on past paper question

Model Answer: Past Paper Question

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  • 1 mark: [Key terminology]
  • 1 mark: [Mechanism/process]
  • 1 mark: [Application/example]
  • 1 mark: [Evaluation - Higher]

Model response: "[Complete answer with expected detail/terminology]"

Why full marks: [What makes this strong]

Stretch & Challenge (Grade 8-9):
  • Synoptic links: Connect to EL1-logic-gates-and-boolean-algebra / EL3-sequential-logic
  • Real-world: Research use in industry, medicine or research
  • Advanced calc: Try a more challenging variant
  • Critical: "Evaluate limitations of today's model"
  • Research: Recent discovery on combinational logic design, summarise 100 words

Plenary (5 mins)

Label the Diagram

Unlabelled diagram - write all parts in 1 min

Assessment Criteria

Lesson 2: Core Concepts: Combinational Logic Design

Duration: 50 minutes

Starter Activity (5 minutes)

Review Previous Lesson

Quick recap: write 3 key points from last lesson on combinational logic design. Use mini-whiteboard or paper.

Main Content (35 minutes)

Parent/Teacher Guide:
Before lesson: Read script below. Prepare materials. Pre-teach key vocab: Combinational Logic Design.
If stuck: See Troubleshooting below. Break into smaller steps.
Extension: See Stretch & Challenge section.
Teaching Script (35 mins):
Mins 0-5 - Hook: "Today: Combinational Logic Design. Goal: by the end you can ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit, using the method shown step by step. Connects to the previous lesson in this unit because you'll reuse its method throughout today's work."
Mins 5-15 - Direct Instruction: 1) Define: "Combinational Logic Design is..." 2) Key principle: "Most important:..." 3) Draw diagram, label live. 4) Real example: "Like ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit. - a real example worked through in full..."
Mins 15-25 - Guided Practice: Ex1: Teacher models. Ex2: Student tries with guidance. Ex3: Student independent.
Mins 25-35 - Independent Practice: 3-5 questions. Immediate feedback.
Worked Example 1: Basic

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. What is asked? Explain
  2. Recall knowledge:
  3. Apply: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous stage, creating a ripple delay proportional to the number of bits.
  4. Check: Check the units named in the question and sense-check the size of your answer.
  5. Answer: State the complete final answer.

Tip: "Show working - method marks > answer marks."

Worked Example 2: Multi-step

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Break down: Separate parts?
  2. Solve each: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous
  3. Combine: The parts chain: each answer feeds the next step of the question.
  4. Final answer: Evidence cited from the lesson content.
Worked Example 3: Data/Application

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Read data: Axes, units, scale
  2. Patterns: Trends, anomalies
  3. Explain: Why? Using combinational logic design
  4. Conclude: Evidence-based

Common Questions & Troubleshooting

Q: "Why does Combinational Logic Design work this way?"
A: Analogy: "✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.". Try re-draw or re-write the worked example from memory, then check it against the model answer.
Q: "Wrong answers on calculations."
A: Checklist: units? formula? calculator mode? sig figs?
Q: "Can't remember key terms."
A: Flashcards (term front, def+diagram back). Spaced repetition: day 1, 3, 7.
Q: "Exam wording confuses me."
A: Commands: Describe=what you see; Explain=reasons; Evaluate=pros/cons+judgement; Calculate=working+units.
Q: "Running out of time."
A: 1 mark/min. Skip hard, return. Attempt all - partial marks count.

Assessment & Model Answers

Mastery Checklist:
  • [ ] Define Combinational Logic Design in own words
  • [ ] Identify features in diagram
  • [ ] Explain process step-by-step
  • [ ] Apply to unfamiliar context
  • [ ] Score 80%+ on past paper question

Model Answer: Past Paper Question

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  • 1 mark: [Key terminology]
  • 1 mark: [Mechanism/process]
  • 1 mark: [Application/example]
  • 1 mark: [Evaluation - Higher]

Model response: "[Complete answer with expected detail/terminology]"

Why full marks: [What makes this strong]

Stretch & Challenge (Grade 8-9):
  • Synoptic links: Connect to EL1-logic-gates-and-boolean-algebra / EL3-sequential-logic
  • Real-world: Research use in industry, medicine or research
  • Advanced calc: Try a more challenging variant
  • Critical: "Evaluate limitations of today's model"
  • Research: Recent discovery on combinational logic design, summarise 100 words

Plenary (5 mins)

Label the Diagram

Unlabelled diagram - write all parts in 1 min

Assessment Criteria

Lesson 3: Application: Combinational Logic Design

Duration: 50 minutes

Starter Activity (5 minutes)

Review Previous Lesson

Quick recap: write 3 key points from last lesson on combinational logic design. Use mini-whiteboard or paper.

Main Content (35 minutes)

Parent/Teacher Guide:
Before lesson: Read script below. Prepare materials. Pre-teach key vocab: Combinational Logic Design.
If stuck: See Troubleshooting below. Break into smaller steps.
Extension: See Stretch & Challenge section.
Teaching Script (35 mins):
Mins 0-5 - Hook: "Today: Combinational Logic Design. Goal: by the end you can ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit, using the method shown step by step. Connects to the previous lesson in this unit because you'll reuse its method throughout today's work."
Mins 5-15 - Direct Instruction: 1) Define: "Combinational Logic Design is..." 2) Key principle: "Most important:..." 3) Draw diagram, label live. 4) Real example: "Like ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit. - a real example worked through in full..."
Mins 15-25 - Guided Practice: Ex1: Teacher models. Ex2: Student tries with guidance. Ex3: Student independent.
Mins 25-35 - Independent Practice: 3-5 questions. Immediate feedback.
Worked Example 1: Basic

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. What is asked? Explain
  2. Recall knowledge:
  3. Apply: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous stage, creating a ripple delay proportional to the number of bits.
  4. Check: Check the units named in the question and sense-check the size of your answer.
  5. Answer: State the complete final answer.

Tip: "Show working - method marks > answer marks."

Worked Example 2: Multi-step

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Break down: Separate parts?
  2. Solve each: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous
  3. Combine: The parts chain: each answer feeds the next step of the question.
  4. Final answer: Evidence cited from the lesson content.
Worked Example 3: Data/Application

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Read data: Axes, units, scale
  2. Patterns: Trends, anomalies
  3. Explain: Why? Using combinational logic design
  4. Conclude: Evidence-based

Common Questions & Troubleshooting

Q: "Why does Combinational Logic Design work this way?"
A: Analogy: "✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.". Try re-draw or re-write the worked example from memory, then check it against the model answer.
Q: "Wrong answers on calculations."
A: Checklist: units? formula? calculator mode? sig figs?
Q: "Can't remember key terms."
A: Flashcards (term front, def+diagram back). Spaced repetition: day 1, 3, 7.
Q: "Exam wording confuses me."
A: Commands: Describe=what you see; Explain=reasons; Evaluate=pros/cons+judgement; Calculate=working+units.
Q: "Running out of time."
A: 1 mark/min. Skip hard, return. Attempt all - partial marks count.

Assessment & Model Answers

Mastery Checklist:
  • [ ] Define Combinational Logic Design in own words
  • [ ] Identify features in diagram
  • [ ] Explain process step-by-step
  • [ ] Apply to unfamiliar context
  • [ ] Score 80%+ on past paper question

Model Answer: Past Paper Question

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  • 1 mark: [Key terminology]
  • 1 mark: [Mechanism/process]
  • 1 mark: [Application/example]
  • 1 mark: [Evaluation - Higher]

Model response: "[Complete answer with expected detail/terminology]"

Why full marks: [What makes this strong]

Stretch & Challenge (Grade 8-9):
  • Synoptic links: Connect to EL1-logic-gates-and-boolean-algebra / EL3-sequential-logic
  • Real-world: Research use in industry, medicine or research
  • Advanced calc: Try a more challenging variant
  • Critical: "Evaluate limitations of today's model"
  • Research: Recent discovery on combinational logic design, summarise 100 words

Plenary (5 mins)

Exam Question Speed Round

5 quick questions, 1 min each. Mark together.

Assessment Criteria

Lesson 4: Exam Practice: Combinational Logic Design

Duration: 50 minutes

Starter Activity (5 minutes)

Review Previous Lesson

Quick recap: write 3 key points from last lesson on combinational logic design. Use mini-whiteboard or paper.

Main Content (35 minutes)

Parent/Teacher Guide:
Before lesson: Read script below. Prepare materials. Pre-teach key vocab: Combinational Logic Design.
If stuck: See Troubleshooting below. Break into smaller steps.
Extension: See Stretch & Challenge section.
Teaching Script (35 mins):
Mins 0-5 - Hook: "Today: Combinational Logic Design. Goal: by the end you can ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit, using the method shown step by step. Connects to the previous lesson in this unit because you'll reuse its method throughout today's work."
Mins 5-15 - Direct Instruction: 1) Define: "Combinational Logic Design is..." 2) Key principle: "Most important:..." 3) Draw diagram, label live. 4) Real example: "Like ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit. - a real example worked through in full..."
Mins 15-25 - Guided Practice: Ex1: Teacher models. Ex2: Student tries with guidance. Ex3: Student independent.
Mins 25-35 - Independent Practice: 3-5 questions. Immediate feedback.
Worked Example 1: Basic

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. What is asked? Explain
  2. Recall knowledge:
  3. Apply: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous stage, creating a ripple delay proportional to the number of bits.
  4. Check: Check the units named in the question and sense-check the size of your answer.
  5. Answer: State the complete final answer.

Tip: "Show working - method marks > answer marks."

Worked Example 2: Multi-step

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Break down: Separate parts?
  2. Solve each: ✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input. ✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous
  3. Combine: The parts chain: each answer feeds the next step of the question.
  4. Final answer: Evidence cited from the lesson content.
Worked Example 3: Data/Application

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  1. Read data: Axes, units, scale
  2. Patterns: Trends, anomalies
  3. Explain: Why? Using combinational logic design
  4. Conclude: Evidence-based

Common Questions & Troubleshooting

Q: "Why does Combinational Logic Design work this way?"
A: Analogy: "✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.". Try re-draw or re-write the worked example from memory, then check it against the model answer.
Q: "Wrong answers on calculations."
A: Checklist: units? formula? calculator mode? sig figs?
Q: "Can't remember key terms."
A: Flashcards (term front, def+diagram back). Spaced repetition: day 1, 3, 7.
Q: "Exam wording confuses me."
A: Commands: Describe=what you see; Explain=reasons; Evaluate=pros/cons+judgement; Calculate=working+units.
Q: "Running out of time."
A: 1 mark/min. Skip hard, return. Attempt all - partial marks count.

Assessment & Model Answers

Mastery Checklist:
  • [ ] Define Combinational Logic Design in own words
  • [ ] Identify features in diagram
  • [ ] Explain process step-by-step
  • [ ] Apply to unfamiliar context
  • [ ] Score 80%+ on past paper question

Model Answer: Past Paper Question

Q: ✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.

  • 1 mark: [Key terminology]
  • 1 mark: [Mechanism/process]
  • 1 mark: [Application/example]
  • 1 mark: [Evaluation - Higher]

Model response: "[Complete answer with expected detail/terminology]"

Why full marks: [What makes this strong]

Stretch & Challenge (Grade 8-9):
  • Synoptic links: Connect to EL1-logic-gates-and-boolean-algebra / EL3-sequential-logic
  • Real-world: Research use in industry, medicine or research
  • Advanced calc: Try a more challenging variant
  • Critical: "Evaluate limitations of today's model"
  • Research: Recent discovery on combinational logic design, summarise 100 words

Plenary (5 mins)

Exam Question Speed Round

5 quick questions, 1 min each. Mark together.

Assessment Criteria

📝 Mark Scheme Guidance

How examiners mark EL2: Read the command word carefully — State = one word/phrase (1 mark), Describe = pattern or detail (2 marks), Explain = reason with "because" (2–3 marks), Compare = similarities AND differences, Evaluate = both sides + conclusion. Method marks are awarded for correct working even if the final answer is wrong. Always show your working — unexplained answers score zero for AO2.

Success on EL2 questions: Underline the command word, count the marks (one mark per point expected), and answer in the format the command word demands.

Board Notes & Revision Links

This lesson is examined by: Eduqas GCSE Electronics. Tier and paper details vary - always check your board's current specification.

Follow-up revision: combinational-logic on GCSE Revise (notes, flashcards and auto-graded target tests for this exact topic).

Homework & Consolidation

Recommended Resources

🎓 Smart Lesson (Guided)