E8: Combinational Logic Systems
Combining logic gates, half adder, full adder, multiplexers and decoders
Combinational Logic Systems
Combining logic gates, half adder, full adder, multiplexers and decoders
Key Fact: Combinational logic produces outputs determined solely by current inputs, with no memory or feedback.
Key Fact: A half adder adds two single-bit binary numbers, producing Sum (XOR) and Carry (AND).
Key Fact: A full adder adds three bits (two inputs plus carry-in), producing Sum and Carry-out using two half adders and an OR gate.
Key Fact: Sum = A ⊕ B ⊕ C_in; Carry-out = A·B + C_in·(A ⊕ B).
Key Fact: Multiple full adders can be cascaded to build multi-bit ripple-carry adders.
Key Fact: A multiplexer (MUX) selects one of several inputs and routes it to a single output, controlled by select lines.
Key Fact: A 2ⁿ-to-1 MUX has n select lines and 2ⁿ data inputs.
Key Fact: A decoder converts a binary input on n lines to one of 2ⁿ output lines being active (e.g. 3-to-8 decoder).
Key Fact: An encoder performs the reverse of a decoder: it converts active input lines into a binary code output.
Key Fact: Priority encoders resolve conflicts when multiple inputs are active by selecting the highest-priority input.
Key Fact: Comparators compare two binary numbers and output whether A > B, A = B or A < B.
Key Fact: Combinational circuits can be analysed by writing the Boolean expression from the gate diagram or deriving a truth table.
📋 Key Vocabulary and Concepts
For Combinational Logic Systems, you must know:
- Half adder: A combinational circuit that adds two single bits, producing a Sum and Carry output.
- Full adder: A combinational circuit that adds three bits (two inputs and a carry-in), producing Sum and Carry-out.
- Multiplexer: A data selector that routes one of several inputs to a single output based on select lines.
- Decoder: A circuit that converts a binary input into one active output line among many.
- Ripple-carry adder: A multi-bit adder built by cascading full adders, where carry propagates from one stage to the next.
- Priority encoder: An encoder that assigns priority to inputs so the highest-priority active input is encoded.
❓ Practice Questions
Q: What logic gates does a half adder use?
Q: How does a full adder differ from a half adder?
Q: How many select lines does an 8-to-1 multiplexer need?
Q: What does a 3-to-8 decoder do?
Q: Write the Boolean expressions for a full adder.
✅ Answers
- An XOR gate for the Sum (A ⊕ B) and an AND gate for the Carry (A · B).
- A full adder includes a carry-in input, allowing it to add three bits (A, B and C_in); a half adder only adds two bits.
- 3 select lines, since 2³ = 8.
- It takes a 3-bit binary input and activates exactly one of its 8 output lines corresponding to that binary value.
- Sum = A ⊕ B ⊕ C_in; Carry-out = A·B + C_in·(A ⊕ B).
🎯 Exam Tips
- When analysing a combinational circuit, work from inputs to outputs, writing expressions at each gate.
- For adder questions, clearly state Sum and Carry expressions separately.
- Remember: a half adder cannot handle carry-in; always use a full adder when carry propagation is needed.
- For MUX questions, identify the number of select lines: n = log₂(number of data inputs).
- Build truth tables for combinational circuits by evaluating each gate step by step.
📝 Exam Technique
GCSE Electronics Exam Tips — Combinational Logic Systems:
1. For Combinational Logic Systems questions, use correct electronic symbols and terminology
2. Always show your working in calculations, including units at each step
3. When analysing circuits, state which law or rule you are applying first
4. For evaluation questions on Combinational Logic Systems, compare component choices and consider cost, reliability and tolerance
5. Draw circuit diagrams neatly with conventional symbols
1. For Combinational Logic Systems questions, use correct electronic symbols and terminology
2. Always show your working in calculations, including units at each step
3. When analysing circuits, state which law or rule you are applying first
4. For evaluation questions on Combinational Logic Systems, compare component choices and consider cost, reliability and tolerance
5. Draw circuit diagrams neatly with conventional symbols
⚠️ Common Errors
✗ Using a half adder where a carry-in from a previous stage is required. ✓ Use a full adder when there is a carry-in input; half adders only work for the least significant bit.
✗ Confusing multiplexer and decoder functions. ✓ A multiplexer selects one input from many to route to an output; a decoder activates one output from many based on a binary input.
✗ Forgetting carry propagation delay in ripple-carry adders. ✓ Each full adder must wait for the carry from the previous stage, creating a ripple delay proportional to the number of bits.
✗ Omitting the OR gate that combines carry terms in a full adder. ✓ Carry-out = A·B + C_in·(A ⊕ B); the two carry terms are combined with an OR gate.
✍️ Model Answer
Full-Mark Response
Describe the structure and operation of a full adder, and explain how multiple full adders are combined to create a multi-bit adder.
A full adder adds three single-bit inputs: A, B and a carry-in (C_in), producing a Sum and Carry-out. The Sum is computed as A ⊕ B ⊕ C_in using two XOR gates. The Carry-out is A·B + C_in·(A ⊕ B), requiring two AND gates and one OR gate. A full adder can be built from two half adders and an OR gate: the first half adder adds A and B to give a partial sum and carry, the second half adder adds the partial sum to C_in, and the OR gate combines the two carry signals. To build a multi-bit (e.g. 4-bit) ripple-carry adder, four full adders are cascaded: the carry-out of each stage connects to the carry-in of the next. The least significant full adder has its C_in set to 0. The result is computed bit by bit, with carries rippling from right to left. This ripple propagation introduces delay — the worst case is when a carry must propagate through all stages — which limits the speed of large adders.
📊 AO Deep Dive
Assessment Objective Analysis
AO1 (Knowledge & Understanding): Demonstrate knowledge and understanding of combinational logic systems, including electronic components, circuit theory and systems concepts relevant to WJEC Eduqas C690QS.
AO2 (Application): Apply knowledge and understanding of combinational logic systems to analyse, design and construct electronic circuits and systems.
AO3 (Evaluation): Evaluate electronic circuits and systems, making reasoned judgements about design choices, performance and practical considerations, constructing supported arguments.
📝 Exam Questions by Topic
🎬 Video Resources
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